LaFonera Hardware IO (en)
From DD-WRT Wiki
You are here: DD-WRT wiki mainpage / LaFonera / Hardware / IO
[edit] Input/Output
In order to create more mods, we need to know what we have to work with electrically. This would mean knowing the function of the pins on J1, J2 and SW1 (and other test points, if they can be usefull to us. In order to get this started, I am putting down what I have found from looking over this site. I would also like to know if anyone has taken the time to make a schmatic of the LaFonera yet? Please fill in the missing information if you know it.
J1 - JTAG header (Much info was found here: http://wiki.openwrt.org/OpenWrtDocs/Customizing/Hardware/JTAG_Cable and here: http://tech.am/2006/10/06/autopsy-of-a-fonera/ )
Pin Name Loc. on AR2315 Function
1 nTRST K15 Reset TAP in Atheros AR2315 (from: Multiple sources)
2 GND Ground (from: Multiple sources)
3 TDI L16 Input to Atheros AR2315 (from: Multiple sources)
4 GND Ground (from: Multiple sources)
5 TDO L17 Output from Atheros AR2315 (from: Multiple sources)
6 GND Ground (from: Multiple sources)
7 TMS M17 Select TAP Mode in AR2315 (from: Multiple sources)
8 GND Ground (from: Multiple sources)
9 TCK L15 Clock signal to AR2315 (from: Multiple sources)
10 GND Ground (from: Multiple sources)
11 nSRST K16 Reset TAP in AR2315 (from: Multiple sources)
12 NO CONNECTION (from: Multiple sources)
13 NO CONNECTION (from: Multiple sources)
14 VCC +3.3V Power (from: Multiple sources)
nTRST 1 2 GND (Pin 1 is a square pad)
TDI 3 4 GND
TDO 5 6 GND
TMS 7 8 GND
TCK 9 10 GND
nSRST 11 12 n/a
n/a 13 14 Vcc
Much JTAG info, including making your own JTAG to parallel port cables and software can be found at: http://wiki.openwrt.org/OpenWrtDocs/Customizing/Hardware/JTAG_Cable
Link to EJTAG specs (from MIPS Technologies) is wrong at the above link, use this instead (you will be required to register - for free - to view): http://www.mips.com/content/Documentation/MIPSDocumentation/ProcessorArchitecture/EJTAG/MD00047-2B-EJTAG-SPC-03.10.pdf
J2 - Serial Port
Pin Name Function 1 2 3 RX 3.3V RS-232 Data into the Fon (from http://www.dd-wrt.com/wiki/index.php/LaFonera_Hardware_Serial-Cable-Port) 4 5 TX 3.3V RS-232 Data from the Fon (from http://www.dd-wrt.com/wiki/index.php/LaFonera_Hardware_Serial-Cable-Port) 6 7 8 9 GND Ground (from http://www.dd-wrt.com/wiki/index.php/LaFonera_Hardware_Serial-Cable-Port) 10 VCC +3.3V from Fon's voltage regulator (from http://www.dd-wrt.com/wiki/index.php/LaFonera_Hardware_Serial-Cable-Port)
SW1 - ???
Pin Name Function (LARGE PAD) - Connected to metal sheild on Ethernet connector 1 GPIO 3 General IO - Used in MMC/SD card hack (from http://kwzs.be/~kevin/ar531x/gpio%20pinout.txt) 2 GPIO 4 General IO - Used in MMC/SD card hack (from http://kwzs.be/~kevin/ar531x/gpio%20pinout.txt) 3 VCC +3.3V Power 4 VCC +3.3V Power 5 GPIO 1 (not 2) General IO - Used in MMC/SD card hack (from http://kwzs.be/~kevin/ar531x/gpio%20pinout.txt) 6 GPIO 7 General IO - Used in MMC/SD card hack (from http://kwzs.be/~kevin/ar531x/gpio%20pinout.txt) (LARGE PAD) - Connected to metal sheild on Ethernet connector
Test Points
Pin Name Function TP1 TP2 TP3 GPIO 0 General IO - Used in MMC/SD card hack (from http://kwzs.be/~kevin/ar531x/gpio%20pinout.txt) TP4 TP5 TP6 TP7 TP8
General I/O used for MMC/SD Mod (from http://kwzs.be/~kevin/ar531x/gpio%20pinout.txt) (link seems to be dead)
GPIO Location of pin in LaFonera 0 TP3 1 pin 5 of SW1 2 WLAN LED 3 pin 1 of SW1 4 pin 2 of SW1 5 RESET (!) 6 RESET button 7 pin 6 of SW1
This page brought to you by Bsb001 23:53, 25 May 2007 (CEST)BSB001